Binary Arithmetic and Adders

Binary arithmetic is the hardware language behind counters, timers, address generators, CPUs, DSP blocks, and FPGA datapaths. The same ideas used to add two 4-bit numbers in a classroom scale directly to 32-bit microcontrollers and 64-bit processors.

Learning Objectives

By the end of this lesson, you should be able to:

Add unsigned binary numbers and track carries.
Explain half adders, full adders, ripple-carry adders, and carry look-ahead adders.
Use two's-complement arithmetic for signed addition and subtraction.
Detect unsigned carry and signed overflow correctly.
Estimate adder delay and choose an adder structure for a practical design.

Binary Addition Rules

Binary addition has only four single-bit cases:

A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

The last row is the important one: 1 + 1 = 10b, so the sum bit is 0 and the carry into the next column is 1.

Worked Example: 11 + 6

  carries: 1 1 1 .
           1 0 1 1   (11 decimal)
         + 0 1 1 0   (6 decimal)
         ---------
         1 0 0 0 1   (17 decimal)

The rightmost bit is the least significant bit. Carries move from right to left, exactly like decimal addition.

Half Adder

A half adder adds two input bits, A and B. It produces a sum bit S and a carry bit C.

A	B	S	C
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

The equations are:

$$
S = A \oplus B
$$

$$
C = A \cdot B
$$

flowchart LR A[A] --> XOR1[XOR] B[B] --> XOR1 A --> AND1[AND] B --> AND1 XOR1 --> S[Sum] AND1 --> C[Carry]

The half adder is useful for the least significant stage when there is no incoming carry. It is not enough for the middle stages of a multi-bit adder because those stages must also add a carry from the previous bit.

Full Adder

A full adder adds three one-bit values: A, B, and carry-in Cin.

A	B	Cin	S	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

The sum is the odd-parity function:

$$
S = A \oplus B \oplus C_{in}
$$

The carry-out is 1 when at least two inputs are 1:

$$
C_{out} = A B + C_{in}(A \oplus B)
$$

Equivalent majority form:

$$
C_{out} = AB + AC_{in} + BC_{in}
$$

flowchart LR A[A] --> HA1[Half Adder] B[B] --> HA1 HA1 -- partial sum --> HA2[Half Adder] CIN[Cin] --> HA2 HA2 --> S[Sum] HA1 -- carry 1 --> OR1[OR] HA2 -- carry 2 --> OR1 OR1 --> COUT[Cout]

Ripple-Carry Adder

The simplest multi-bit adder chains full adders. Each carry-out becomes the carry-in of the next more significant bit.

flowchart LR C0[Cin] --> FA0["FA0\nA0+B0"] FA0 --> S0[S0] FA0 -- C1 --> FA1["FA1\nA1+B1"] FA1 --> S1[S1] FA1 -- C2 --> FA2["FA2\nA2+B2"] FA2 --> S2[S2] FA2 -- C3 --> FA3["FA3\nA3+B3"] FA3 --> S3[S3] FA3 -- C4 --> COUT[Cout]

Ripple adders are compact and easy to understand. Their weakness is delay: the most significant sum bit cannot settle until the carry has passed through all lower stages.

If one full-adder carry stage has delay tFA, an approximate worst-case delay for an n-bit ripple adder is:

$$
t_{ripple} \approx n \cdot t_{FA}
$$

Example: a 32-bit ripple adder with tFA = 0.8 ns has a worst-case carry delay near 25.6 ns. That is too slow for many high-speed CPUs, but it may be fine in a small microcontroller peripheral or low-speed FPGA control path.

Carry Look-Ahead

Carry look-ahead adders reduce delay by computing carry signals from generate and propagate terms.

For bit i:

$$
G_i = A_iB_i
$$

$$
P_i = A_i \oplus B_i
$$

Gi means the bit position generates a carry by itself. Pi means it will propagate an incoming carry.

For a 4-bit block, the carry terms expand from the recurrence Cnext = G + P Cin:

$$
C_1 = G_0 + P_0C_0
$$

$$
C_2 = G_1 + P_1G_0 + P_1P_0C_0
$$

The next two carry equations continue the same pattern:

C3 = G2 + P2 C2
C4 = G3 + P3 C3

Expanded forms are useful for gate-level design, but on small screens the recurrence is easier to read and is usually how engineers reason about a carry-look-ahead block before generating the full logic.

flowchart TD AB["A[3:0], B[3:0]"] --> GP["Generate and propagate\nGi=AiBi, Pi=Ai xor Bi"] C0[Cin] --> CLA["Carry look-ahead logic"] GP --> CLA CLA --> CARRIES["C1, C2, C3, C4"] GP --> SUM["Sum logic\nSi=Pi xor Ci"] CARRIES --> SUM

Carry look-ahead uses more gates and wiring, but the carry computation is much shallower than ripple carry. Real processors often use hierarchical adders such as carry look-ahead, carry select, Brent-Kung, or Kogge-Stone structures.

Unsigned Carry vs Signed Overflow

Do not confuse carry with overflow. They answer different questions.

Flag	Applies To	Meaning
Carry `C`	Unsigned arithmetic	Result exceeded the available bit width
Overflow `V`	Signed two's-complement arithmetic	Result is outside signed range

For unsigned 4-bit addition, 1111 + 0001 = 1_0000. The lower 4 bits are 0000 and carry is 1, meaning the correct unsigned result needs 5 bits.

For signed 4-bit two's-complement addition, the range is -8 to +7. Adding 0110 (+6) and 0101 (+5) gives 1011, which looks like -5. That is signed overflow because two positive inputs produced a negative output.

Signed overflow can be detected by:

$$
V = C_{in,MSB} \oplus C_{out,MSB}
$$

It can also be detected from signs: overflow occurs when the input sign bits match and the result sign bit is different. In Boolean form, use same input signs AND result sign changed.

Two's-Complement Subtraction

Two's complement represents signed numbers using the same adder hardware as unsigned arithmetic.

For an n-bit number:

$$
\text{range} = -2^{n-1} \text{ to } 2^{n-1}-1
$$

To negate a number:

Invert every bit.
Add 1.

Example: find -5 in 4 bits.

 +5 = 0101
invert 1010
add 1 1011
 -5 = 1011

Subtraction becomes addition:

$$
A - B = A + (\overline{B} + 1)
$$

In hardware, an adder/subtractor usually XORs each B bit with a subtract control signal and uses the same signal as the carry-in.

flowchart LR SUB[SUB control] --> XORB0["B0 xor SUB"] SUB --> XORB1["B1 xor SUB"] SUB --> CIN[Cin] A0[A0] --> ADDER["n-bit adder"] A1[A1..An] --> ADDER XORB0 --> ADDER XORB1 --> ADDER CIN --> ADDER ADDER --> S[Result] ADDER --> FLAGS[Carry and overflow flags]

When SUB = 0, the circuit adds A + B. When SUB = 1, it adds A + not(B) + 1, which is A - B.

Binary Multiplication Basics

Binary multiplication is repeated shift-and-add. If a multiplier bit is 1, add a shifted copy of the multiplicand. If it is 0, add zero.

Example: 1011b x 1101b = 11 x 13.

         1011
       x 1101
       ------
         1011
        0000.
       1011..
      1011...
      --------
      10001111  (143 decimal)

Hardware multipliers use many adders. Small controllers may use sequential shift-add hardware. DSPs, CPUs, and FPGAs often use parallel multiplier structures or dedicated DSP blocks.

Practical Design Checks

Size the result correctly. Adding two n-bit unsigned numbers can require n+1 bits.
Use signed types only when the signal is truly signed.
Check both carry and overflow in CPU flag examples.
In HDL, declare widths explicitly; accidental truncation is a common source of bugs.
For FPGA datapaths, pipeline wide adders when the timing report shows carry-chain delay near the clock limit.

Common Mistakes

Treating Cout as signed overflow.
Forgetting to discard the final carry in fixed-width two's-complement subtraction.
Mixing signed and unsigned values without extending the sign bit.
Estimating ripple delay from average cases instead of worst-case carry propagation.
Writing HDL expressions where the result width silently follows the narrowest operand.

Practice

Add 10110101b + 01011110b and show the carry chain.
Find the 8-bit two's complement of 01101001b.
Compute 0110b - 1001b using 4-bit two's-complement arithmetic.
A 16-bit ripple adder has tFA = 1.2 ns. Estimate worst-case carry delay.
Decide whether each case has unsigned carry, signed overflow, both, or neither: 0111+0001, 1111+0001, 1000+1000.

Summary

Binary adders are built from simple logic, but the design details matter. Half adders handle two bits, full adders add carry-in, ripple adders are compact but delay grows with width, and carry look-ahead reduces delay by computing carries in parallel. Two's-complement arithmetic lets the same adder perform signed addition and subtraction, provided you interpret carry and overflow correctly.

Mind Map

mindmap root((Binary Adders)) Core Add bits with sum and carry Half adder has no Cin Full adder includes Cin Equations Half S equals A xor B Half C equals A and B Full S equals A xor B xor Cin Cout equals AB plus Cin times A xor B Ripple delay about n times tFA Architectures Ripple carry is small CLA uses generate and propagate Carry select trades area for speed DSP blocks multiply faster Signed math Two complement range minus 2 to n minus 1 Negate by invert plus one Subtract as A plus not B plus one Overflow equals Cin MSB xor Cout MSB Practical checks Extend result width Keep signed and unsigned separate Verify flag meaning Pipeline wide FPGA adders Common mistakes Carry used as overflow Silent HDL truncation Missing sign extension Ignoring worst case carry